diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index f610d40..53efcd4 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-tve1205g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-videostrong-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-vr-android.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
 
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-box-plus-dram-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-box-plus-dram-timing.dtsi
new file mode 100644
index 0000000..59cae37
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-box-plus-dram-timing.dtsi
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/memory/rk3328-dram.h>
+
+/ {
+	ddr_timing: ddr_timing {
+		compatible = "rockchip,ddr-timing";
+		ddr3_speed_bin = <DDR3_DEFAULT>;
+		ddr4_speed_bin = <DDR4_DEFAULT>;
+		pd_idle = <0>;
+		sr_idle = <0>;
+		sr_mc_gate_idle = <0>;
+		srpd_lite_idle	= <0>;
+		standby_idle = <0>;
+
+		auto_pd_dis_freq = <1066>;
+		auto_sr_dis_freq = <800>;
+		ddr3_dll_dis_freq = <300>;
+		ddr4_dll_dis_freq = <625>;
+		phy_dll_dis_freq = <400>;
+
+		ddr3_odt_dis_freq = <100>;
+		phy_ddr3_odt_dis_freq = <100>;
+		ddr3_drv = <DDR3_DS_40ohm>;
+		ddr3_odt = <DDR3_ODT_120ohm>;
+		phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
+		phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
+		phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
+		phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
+
+		lpddr3_odt_dis_freq = <666>;
+		phy_lpddr3_odt_dis_freq = <666>;
+		lpddr3_drv = <LP3_DS_40ohm>;
+		lpddr3_odt = <LP3_ODT_240ohm>;
+		phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+		phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+		phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+		phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+		lpddr4_odt_dis_freq = <800>;
+		phy_lpddr4_odt_dis_freq = <800>;
+		lpddr4_drv = <LP4_PDDS_60ohm>;
+		lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
+		lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
+		phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
+		phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+		phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+		phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
+
+		ddr4_odt_dis_freq = <666>;
+		phy_ddr4_odt_dis_freq = <666>;
+		ddr4_drv = <DDR4_DS_34ohm>;
+		ddr4_odt = <DDR4_RTT_NOM_120ohm>;
+		phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_25ohm>;
+		phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_25ohm>;
+		phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_25ohm>;
+		phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_120ohm>;
+
+		/* CA de-skew, one step is 47.8ps, range 0-15 */
+		ddr3a1_ddr4a9_de-skew = <1>;
+		ddr3a0_ddr4a10_de-skew = <1>;
+		ddr3a3_ddr4a6_de-skew = <0>;
+		ddr3a2_ddr4a4_de-skew = <1>;
+		ddr3a5_ddr4a8_de-skew = <0>;
+		ddr3a4_ddr4a5_de-skew = <1>;
+		ddr3a7_ddr4a11_de-skew = <1>;
+		ddr3a6_ddr4a7_de-skew = <0>;
+		ddr3a9_ddr4a0_de-skew = <1>;
+		ddr3a8_ddr4a13_de-skew = <0>;
+		ddr3a11_ddr4a3_de-skew = <2>;
+		ddr3a10_ddr4cs0_de-skew = <3>;
+		ddr3a13_ddr4a2_de-skew = <1>;
+		ddr3a12_ddr4ba1_de-skew = <0>;
+		ddr3a15_ddr4odt0_de-skew = <3>;
+		ddr3a14_ddr4a1_de-skew = <2>;
+		ddr3ba1_ddr4a15_de-skew = <1>;
+		ddr3ba0_ddr4bg0_de-skew = <1>;
+		ddr3ras_ddr4cke_de-skew = <3>;
+		ddr3ba2_ddr4ba0_de-skew = <1>;
+		ddr3we_ddr4bg1_de-skew = <3>;
+		ddr3cas_ddr4a12_de-skew = <1>;
+		ddr3ckn_ddr4ckn_de-skew = <4>;
+		ddr3ckp_ddr4ckp_de-skew = <4>;
+		ddr3cke_ddr4a16_de-skew = <1>;
+		ddr3odt0_ddr4a14_de-skew = <1>;
+		ddr3cs0_ddr4act_de-skew = <2>;
+		ddr3reset_ddr4reset_de-skew = <3>;
+		ddr3cs1_ddr4cs1_de-skew = <2>;
+		ddr3odt1_ddr4odt1_de-skew = <2>;
+
+		/* DATA de-skew
+		 * RX one step is 25.1ps, range 0-15
+		 * TX one step is 47.8ps, range 0-15
+		 */
+		cs0_dm0_rx_de-skew = <8>;
+		cs0_dm0_tx_de-skew = <9>;
+		cs0_dq0_rx_de-skew = <8>;
+		cs0_dq0_tx_de-skew = <9>;
+		cs0_dq1_rx_de-skew = <8>;
+		cs0_dq1_tx_de-skew = <9>;
+		cs0_dq2_rx_de-skew = <8>;
+		cs0_dq2_tx_de-skew = <9>;
+		cs0_dq3_rx_de-skew = <8>;
+		cs0_dq3_tx_de-skew = <9>;
+		cs0_dq4_rx_de-skew = <8>;
+		cs0_dq4_tx_de-skew = <9>;
+		cs0_dq5_rx_de-skew = <8>;
+		cs0_dq5_tx_de-skew = <9>;
+		cs0_dq6_rx_de-skew = <8>;
+		cs0_dq6_tx_de-skew = <9>;
+		cs0_dq7_rx_de-skew = <8>;
+		cs0_dq7_tx_de-skew = <9>;
+		cs0_dqs0_rx_de-skew = <7>;
+		cs0_dqs0p_tx_de-skew = <10>;
+		cs0_dqs0n_tx_de-skew = <10>;
+
+		cs0_dm1_rx_de-skew = <8>;
+		cs0_dm1_tx_de-skew = <8>;
+		cs0_dq8_rx_de-skew = <8>;
+		cs0_dq8_tx_de-skew = <9>;
+		cs0_dq9_rx_de-skew = <8>;
+		cs0_dq9_tx_de-skew = <8>;
+		cs0_dq10_rx_de-skew = <8>;
+		cs0_dq10_tx_de-skew = <9>;
+		cs0_dq11_rx_de-skew = <8>;
+		cs0_dq11_tx_de-skew = <8>;
+		cs0_dq12_rx_de-skew = <8>;
+		cs0_dq12_tx_de-skew = <9>;
+		cs0_dq13_rx_de-skew = <8>;
+		cs0_dq13_tx_de-skew = <8>;
+		cs0_dq14_rx_de-skew = <8>;
+		cs0_dq14_tx_de-skew = <9>;
+		cs0_dq15_rx_de-skew = <8>;
+		cs0_dq15_tx_de-skew = <8>;
+		cs0_dqs1_rx_de-skew = <8>;
+		cs0_dqs1p_tx_de-skew = <10>;
+		cs0_dqs1n_tx_de-skew = <10>;
+
+		cs0_dm2_rx_de-skew = <8>;
+		cs0_dm2_tx_de-skew = <9>;
+		cs0_dq16_rx_de-skew = <8>;
+		cs0_dq16_tx_de-skew = <9>;
+		cs0_dq17_rx_de-skew = <8>;
+		cs0_dq17_tx_de-skew = <9>;
+		cs0_dq18_rx_de-skew = <8>;
+		cs0_dq18_tx_de-skew = <9>;
+		cs0_dq19_rx_de-skew = <8>;
+		cs0_dq19_tx_de-skew = <9>;
+		cs0_dq20_rx_de-skew = <8>;
+		cs0_dq20_tx_de-skew = <9>;
+		cs0_dq21_rx_de-skew = <8>;
+		cs0_dq21_tx_de-skew = <9>;
+		cs0_dq22_rx_de-skew = <8>;
+		cs0_dq22_tx_de-skew = <9>;
+		cs0_dq23_rx_de-skew = <8>;
+		cs0_dq23_tx_de-skew = <9>;
+		cs0_dqs2_rx_de-skew = <7>;
+		cs0_dqs2p_tx_de-skew = <10>;
+		cs0_dqs2n_tx_de-skew = <10>;
+
+		cs0_dm3_rx_de-skew = <8>;
+		cs0_dm3_tx_de-skew = <8>;
+		cs0_dq24_rx_de-skew = <8>;
+		cs0_dq24_tx_de-skew = <9>;
+		cs0_dq25_rx_de-skew = <8>;
+		cs0_dq25_tx_de-skew = <8>;
+		cs0_dq26_rx_de-skew = <8>;
+		cs0_dq26_tx_de-skew = <8>;
+		cs0_dq27_rx_de-skew = <8>;
+		cs0_dq27_tx_de-skew = <8>;
+		cs0_dq28_rx_de-skew = <8>;
+		cs0_dq28_tx_de-skew = <8>;
+		cs0_dq29_rx_de-skew = <8>;
+		cs0_dq29_tx_de-skew = <8>;
+		cs0_dq30_rx_de-skew = <8>;
+		cs0_dq30_tx_de-skew = <8>;
+		cs0_dq31_rx_de-skew = <8>;
+		cs0_dq31_tx_de-skew = <8>;
+		cs0_dqs3_rx_de-skew = <8>;
+		cs0_dqs3p_tx_de-skew = <10>;
+		cs0_dqs3n_tx_de-skew = <10>;
+
+		cs1_dm0_rx_de-skew = <8>;
+		cs1_dm0_tx_de-skew = <9>;
+		cs1_dq0_rx_de-skew = <8>;
+		cs1_dq0_tx_de-skew = <9>;
+		cs1_dq1_rx_de-skew = <8>;
+		cs1_dq1_tx_de-skew = <9>;
+		cs1_dq2_rx_de-skew = <8>;
+		cs1_dq2_tx_de-skew = <9>;
+		cs1_dq3_rx_de-skew = <8>;
+		cs1_dq3_tx_de-skew = <9>;
+		cs1_dq4_rx_de-skew = <8>;
+		cs1_dq4_tx_de-skew = <9>;
+		cs1_dq5_rx_de-skew = <8>;
+		cs1_dq5_tx_de-skew = <9>;
+		cs1_dq6_rx_de-skew = <8>;
+		cs1_dq6_tx_de-skew = <9>;
+		cs1_dq7_rx_de-skew = <8>;
+		cs1_dq7_tx_de-skew = <9>;
+		cs1_dqs0_rx_de-skew = <7>;
+		cs1_dqs0p_tx_de-skew = <10>;
+		cs1_dqs0n_tx_de-skew = <10>;
+
+		cs1_dm1_rx_de-skew = <8>;
+		cs1_dm1_tx_de-skew = <8>;
+		cs1_dq8_rx_de-skew = <8>;
+		cs1_dq8_tx_de-skew = <9>;
+		cs1_dq9_rx_de-skew = <8>;
+		cs1_dq9_tx_de-skew = <8>;
+		cs1_dq10_rx_de-skew = <8>;
+		cs1_dq10_tx_de-skew = <9>;
+		cs1_dq11_rx_de-skew = <8>;
+		cs1_dq11_tx_de-skew = <8>;
+		cs1_dq12_rx_de-skew = <8>;
+		cs1_dq12_tx_de-skew = <9>;
+		cs1_dq13_rx_de-skew = <8>;
+		cs1_dq13_tx_de-skew = <8>;
+		cs1_dq14_rx_de-skew = <8>;
+		cs1_dq14_tx_de-skew = <9>;
+		cs1_dq15_rx_de-skew = <8>;
+		cs1_dq15_tx_de-skew = <8>;
+		cs1_dqs1_rx_de-skew = <8>;
+		cs1_dqs1p_tx_de-skew = <10>;
+		cs1_dqs1n_tx_de-skew = <10>;
+
+		cs1_dm2_rx_de-skew = <8>;
+		cs1_dm2_tx_de-skew = <9>;
+		cs1_dq16_rx_de-skew = <8>;
+		cs1_dq16_tx_de-skew = <9>;
+		cs1_dq17_rx_de-skew = <8>;
+		cs1_dq17_tx_de-skew = <9>;
+		cs1_dq18_rx_de-skew = <8>;
+		cs1_dq18_tx_de-skew = <9>;
+		cs1_dq19_rx_de-skew = <8>;
+		cs1_dq19_tx_de-skew = <9>;
+		cs1_dq20_rx_de-skew = <8>;
+		cs1_dq20_tx_de-skew = <9>;
+		cs1_dq21_rx_de-skew = <8>;
+		cs1_dq21_tx_de-skew = <9>;
+		cs1_dq22_rx_de-skew = <8>;
+		cs1_dq22_tx_de-skew = <9>;
+		cs1_dq23_rx_de-skew = <8>;
+		cs1_dq23_tx_de-skew = <9>;
+		cs1_dqs2_rx_de-skew = <7>;
+		cs1_dqs2p_tx_de-skew = <10>;
+		cs1_dqs2n_tx_de-skew = <10>;
+
+		cs1_dm3_rx_de-skew = <8>;
+		cs1_dm3_tx_de-skew = <8>;
+		cs1_dq24_rx_de-skew = <8>;
+		cs1_dq24_tx_de-skew = <9>;
+		cs1_dq25_rx_de-skew = <8>;
+		cs1_dq25_tx_de-skew = <8>;
+		cs1_dq26_rx_de-skew = <8>;
+		cs1_dq26_tx_de-skew = <8>;
+		cs1_dq27_rx_de-skew = <8>;
+		cs1_dq27_tx_de-skew = <8>;
+		cs1_dq28_rx_de-skew = <8>;
+		cs1_dq28_tx_de-skew = <8>;
+		cs1_dq29_rx_de-skew = <8>;
+		cs1_dq29_tx_de-skew = <8>;
+		cs1_dq30_rx_de-skew = <8>;
+		cs1_dq30_tx_de-skew = <8>;
+		cs1_dq31_rx_de-skew = <8>;
+		cs1_dq31_tx_de-skew = <8>;
+		cs1_dqs3_rx_de-skew = <8>;
+		cs1_dqs3p_tx_de-skew = <10>;
+		cs1_dqs3n_tx_de-skew = <10>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
new file mode 100644
index 0000000..ac747a6
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -0,0 +1,833 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+#include <dt-bindings/input/input.h>
+#include "rk3328-box-plus-dram-timing.dtsi"
+
+/ {
+	model = "Firefly ROC-RK3328-CC";
+	compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
+	chosen {
+		bootargs = "rockchip_jtag earlyprintk=uart8250-32bit,0xff130000";
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,signal-irq = <159>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <0>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+		status = "okay";
+	};
+
+	gmac_clkin: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac_clkin";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "rockchip,rk3328";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&codec>;
+		};
+	};
+
+	hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <128>;
+		simple-audio-card,name = "rockchip,hdmi";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+	};
+
+	spdif-sound {
+	  status = "disabled";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "rockchip,spdif";
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+	  status = "disabled";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0m1_gpio>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vccio_sd: sdmmcio-regulator {
+		compatible = "regulator-gpio";
+		gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x1
+				  3300000 0x0>;
+		//pinctrl-names = "default";
+		//pinctrl-0 = <&sd_pwr_1800_sel>;
+		regulator-name = "vccio_sd";
+		regulator-type = "voltage";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+	};
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+	};
+
+	wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6354";
+		sdio_vref = <1800>;
+		WIFI,host_wake_irq = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		power {
+			label = "firefly:blue:power";
+			linux,default-trigger = "ir-power-click";
+			gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+			mode = <0x23>;
+		};
+
+		user {
+			label = "firefly:yellow:user";
+            linux,default-trigger = "ir-user-click";
+			gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			mode = <0x05>;
+		};
+
+		ir {
+			status = "disabled";
+			/* gpios = <&gpio2 GPIO_C2 GPIO_ACTIVE_HIGH>; */
+			linux,default-trigger = "ir";
+			default-state = "off";
+			mode = <0x00>;
+		};
+	};
+};
+
+&codec {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+	status = "okay";
+};
+
+&dmc {
+	status = "okay";
+	center-supply = <&vdd_logic>;
+
+	system-status-freq = <
+		/*system status         freq(KHz)*/
+		SYS_STATUS_NORMAL       1066000
+		SYS_STATUS_REBOOT       1066000
+		SYS_STATUS_SUSPEND      1066000
+		SYS_STATUS_VIDEO_1080P  1066000
+		SYS_STATUS_VIDEO_4K     1066000
+		SYS_STATUS_VIDEO_4K_10B 1066000
+		SYS_STATUS_PERFORMANCE  1066000
+		SYS_STATUS_BOOST        1066000
+	>;
+};
+
+&dmc_opp_table {
+	status = "okay";
+
+	rockchip,leakage-voltage-sel = <
+		1   8     0
+		9   254   0
+	>;
+
+	opp-400000000 {
+		status = "disabled";
+	};
+	opp-600000000 {
+		status = "disabled";
+	};
+
+	opp-933000000 {
+		opp-hz = /bits/ 64 <933000000>;
+		opp-microvolt = <1150000>;
+		opp-microvolt-L0 = <1150000>;
+		opp-microvolt-L1 = <1100000>;
+	};
+	opp-1066000000 {
+		opp-hz = /bits/ 64 <1066000000>;
+		opp-microvolt = <1200000>;
+		opp-microvolt-L0 = <1200000>;
+		opp-microvolt-L1 = <1175000>;
+	};
+};
+
+
+&cpu0_opp_table {
+
+	rockchip,leakage-voltage-sel = <
+		1   8     0
+		9   254   1
+	>;
+	nvmem-cells = <&cpu_leakage>;
+	nvmem-cell-names = "cpu_leakage";
+
+	opp-408000000 {
+		opp-hz = /bits/ 64 <408000000>;
+		opp-microvolt = <975000>;
+		opp-microvolt-L0 = <975000>;
+		opp-microvolt-L1 = <950000>;
+		clock-latency-ns = <40000>;
+		opp-suspend;
+	};
+	opp-600000000 {
+		opp-hz = /bits/ 64 <600000000>;
+		opp-microvolt = <975000>;
+		opp-microvolt-L0 = <975000>;
+		opp-microvolt-L1 = <950000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-816000000 {
+		opp-hz = /bits/ 64 <816000000>;
+		opp-microvolt = <1025000>;
+		opp-microvolt-L0 = <1025000>;
+		opp-microvolt-L1 = <1000000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1008000000 {
+		opp-hz = /bits/ 64 <1008000000>;
+		opp-microvolt = <1125000>;
+		opp-microvolt-L0 = <1125000>;
+		opp-microvolt-L1 = <1100000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1200000000 {
+		opp-hz = /bits/ 64 <1200000000>;
+		opp-microvolt = <1250000>;
+		opp-microvolt-L0 = <1250000>;
+		opp-microvolt-L1 = <1225000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1296000000 {
+		opp-hz = /bits/ 64 <1296000000>;
+		opp-microvolt = <1325000>;
+		opp-microvolt-L0 = <1325000>;
+		opp-microvolt-L1 = <1300000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1392000000 {
+		opp-hz = /bits/ 64 <1392000000>;
+		opp-microvolt = <1350000>;
+		opp-microvolt-L0 = <1350000>;
+		opp-microvolt-L1 = <1325000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1512000000 {
+		status = "disabled";
+		opp-hz = /bits/ 64 <1512000000>;
+		opp-microvolt = <1350000>;
+		opp-microvolt-L0 = <1350000>;
+		opp-microvolt-L1 = <1325000>;
+		clock-latency-ns = <40000>;
+	};
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	supports-emmc;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+	status = "okay";
+};
+
+&gmac2io {
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmiim1_pins>;
+	tx_delay = <0x25>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gmac2phy {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "output";
+	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+	assigned-clock-rate = <50000000>;
+	assigned-clocks = <&cru SCLK_MAC2PHY>;
+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+	status = "disabled";
+};
+
+&gpu {
+	status = "okay";
+	mali-supply = <&vdd_logic>;
+};
+
+&gpu_opp_table {
+
+	rockchip,leakage-voltage-sel = <
+		1   8     0                 
+		9   254   1
+	>;
+	nvmem-cells = <&logic_leakage>;
+	nvmem-cell-names = "gpu_leakage";
+
+	opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1050000>;
+			opp-microvolt-L0 = <1050000>;
+			opp-microvolt-L1 = <1025000>;
+	};
+	opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000>;
+			opp-microvolt-L0 = <1050000>;
+			opp-microvolt-L1 = <1025000>;
+	};
+	opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000>;
+			opp-microvolt-L0 = <1050000>;
+			opp-microvolt-L1 = <1025000>;
+	};
+	opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <1125000>;
+			opp-microvolt-L0 = <1125000>;
+			opp-microvolt-L1 = <1100000>;
+	};
+};
+
+&hdmi {
+	#sound-dai-cells = <0>;
+	ddc-i2c-scl-high-time-ns = <9625>;
+	ddc-i2c-scl-low-time-ns = <10000>;
+	status = "okay";
+};
+
+&hdmiphy {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk805: rk805@18 {
+		compatible = "rockchip,rk805";
+		status = "okay";
+		reg = <0x18>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		gpio-controller;
+		#gpio-cells = <2>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+
+		rtc {
+			status = "okay";
+		};
+
+		pwrkey {
+			status = "disabled";
+		};
+
+		gpio {
+			status = "okay";
+		};
+
+		regulators {
+			compatible = "rk805-regulator";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vdd_logic: RK805_DCDC1@0 {
+				regulator-compatible = "RK805_DCDC1";
+				regulator-name = "vdd_logic";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-initial-mode = <0x1>;
+				regulator-ramp-delay = <12500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-mode = <0x2>;
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: RK805_DCDC2@1 {
+				regulator-compatible = "RK805_DCDC2";
+				regulator-name = "vdd_arm";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-initial-mode = <0x1>;
+				regulator-ramp-delay = <12500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-mode = <0x2>;
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: RK805_DCDC3@2 {
+				regulator-compatible = "RK805_DCDC3";
+				regulator-name = "vcc_ddr";
+				regulator-initial-mode = <0x1>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-mode = <0x2>;
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: RK805_DCDC4@3 {
+				regulator-compatible = "RK805_DCDC4";
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-initial-mode = <0x1>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-mode = <0x2>;
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vdd_18: RK805_LDO1@4 {
+				regulator-compatible = "RK805_LDO1";
+				regulator-name = "vdd_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_18emmc: RK805_LDO2@5 {
+				regulator-compatible = "RK805_LDO2";
+				regulator-name = "vcc_18emmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: RK805_LDO3@6 {
+				regulator-compatible = "RK805_LDO3";
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&h265e {
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	rockchip,bclk-fs = <128>;
+	status = "okay";
+};
+
+&i2s1 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	vccio1-supply = <&vcc_io>;
+	vccio2-supply = <&vcc_18emmc>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vdd_18>;
+	vccio5-supply = <&vcc_io>;
+	vccio6-supply = <&vcc_io>;
+	pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+		rockchip,pins =
+			<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;	/* gpio1_d0 */
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+		rockchip,pins =
+			<1 18 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_host {
+		host_vbus_drv: host-vbus-drv {
+		rockchip,pins =
+			<1 26 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+/*
+  sdmmcio-regulator {
+    sd_pwr_1800_sel: sd-pwr-1800-sel {
+			rockchip,pins = 
+        <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+  };
+*/
+
+};
+
+&rkvdec {
+	status = "okay";
+};
+
+&sdio {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <150000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	supports-sdio;
+	status = "disabled";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	sd-uhs-sdr104;
+	disable-wp;
+	clock-freq-min-max = <400000 150000000>;
+	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+	supports-sd;
+	status = "okay";
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+};
+
+&spdif {
+	#sound-dai-cells = <0>;
+	status = "disabled";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy {
+	otg-vbus-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	u2phy_host: host-port {
+		status = "okay";
+	};
+
+	u2phy_otg: otg-port {
+		status = "okay";
+	};
+};
+
+&u3phy {
+	vbus-drv-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&u3phy_utmi {
+	status = "okay";
+};
+
+&u3phy_pipe {
+	status = "okay";
+};
+
+&usb20_otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usbdrd3 {
+	status = "okay";
+};
+
+&usbdrd_dwc3 {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vpu_service {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+	compatible = "rockchip,remotectl-pwm";
+	remote_pwm_id = <3>;
+	handle_cpu_id = <1>;
+	remote_support_psci = <1>;
+
+	ir_key1 {
+		rockchip,usercode = <0x4040>;
+		rockchip,key_table =
+			<0xf2	KEY_REPLY>,
+			<0xba	KEY_BACK>,
+			<0xf4	KEY_UP>,
+			<0xf1	KEY_DOWN>,
+			<0xef	KEY_LEFT>,
+			<0xee	KEY_RIGHT>,
+			<0xbd	KEY_HOME>,
+			<0xea	KEY_VOLUMEUP>,
+			<0xe3	KEY_VOLUMEDOWN>,
+			<0xe2	KEY_SEARCH>,
+			<0xb2	KEY_POWER>,
+			<0xbc	KEY_MUTE>,
+			<0xec	KEY_MENU>,
+			<0xbf	0x190>,
+			<0xe0	0x191>,
+			<0xe1	0x192>,
+			<0xe9	183>,
+			<0xe6	248>,
+			<0xe8	185>,
+			<0xe7	186>,
+			<0xf0	388>,
+			<0xbe	0x175>;
+	};
+
+	ir_key2 {
+        rockchip,usercode = <0xff00>;
+        rockchip,key_table =
+            <0xeb   KEY_POWER>,
+            <0xec   KEY_COMPOSE>,
+            <0xfe   KEY_BACK>,
+            <0xb7   KEY_HOME>,
+            <0xa3   KEY_WWW>,
+            <0xf4   KEY_VOLUMEUP>,
+            <0xa7   KEY_VOLUMEDOWN>,
+            <0xf8   KEY_ENTER>,
+            <0xfc   KEY_UP>,
+            <0xfd   KEY_DOWN>,
+            <0xf1   KEY_LEFT>,
+            <0xe5   KEY_RIGHT>;
+    };
+
+	ir_key3 {
+		rockchip,usercode = <0x1dcc>;
+		rockchip,key_table =
+			<0xee	KEY_REPLY>,
+			<0xf0	KEY_BACK>,
+			<0xf8	KEY_UP>,
+			<0xbb	KEY_DOWN>,
+			<0xef	KEY_LEFT>,
+			<0xed	KEY_RIGHT>,
+			<0xfc	KEY_HOME>,
+			<0xf1	KEY_VOLUMEUP>,
+			<0xfd	KEY_VOLUMEDOWN>,
+			<0xb7	KEY_SEARCH>,
+			<0xff	KEY_POWER>,
+			<0xf3	KEY_MUTE>,
+			<0xbf	KEY_MENU>,
+			<0xf9	0x191>,
+			<0xf5	0x192>,
+			<0xb3	388>,
+			<0xbe	KEY_1>,
+			<0xba	KEY_2>,
+			<0xb2	KEY_3>,
+			<0xbd	KEY_4>,
+			<0xf9	KEY_5>,
+			<0xb1	KEY_6>,
+			<0xfc	KEY_7>,
+			<0xf8	KEY_8>,
+			<0xb0	KEY_9>,
+			<0xb6	KEY_0>,
+			<0xb5	KEY_BACKSPACE>;
+	};
+};
